San Jose, Calif. (Gawkwire.com) Renesas Technology America, Inc. today announced an enhanced SH7786 dual-core 32-bit processor, a second-generation version fabricated with a 65-nm process for high-performance multimedia equipment such as car navigation systems. The new processor delivers excellent processing performance: up to 1,920 million instructions per second (MIPS) when operating at 533MHz. This member of the SuperH® family incorporates a DDR3-SDRAM memory interface for faster, ultrahigh-speed data transfers: up to 4.27Gbytes per second (4.27GB/s). Yet the device uses less power than the previous version, which was fabricated with a 90-nm process.
Paul Sykes, Marketing Manager, MPU Group, Renesas Technology America, Inc., said, “With its dual SH-4A high-performance 32-bit RISC CPU cores, each of which delivers up to 960 MIPS performance, the SH7786 can process complex data at high speeds for excellent application response. It readily meets the requirements of next-generation car navigation systems that have functions such as graphical display capabilities, high-quality audio reproduction, and image recognition. The faster data-transfer capabilities of the new chip help ensure that the user’s experience is exceptionally impressive, while the decreased power consumption eliminates the need to build bigger power supplies, increase heat-sink size and use larger power wires.”
“Besides car navigation systems, we expect that this processor will be advantageous to customers that are producing game consoles, digital home electronics, and industrial equipment, among other applications,” Sykes added.
The new SH7786 integrates a dedicated 32-bit bus operating at 533MHz for connecting to DDR3-SDRAM (Double Data Rate 3-Synchronous DRAM) with an operating voltage of 1.5V, enabling the fast 4.27GB/s transfer rates. (Earlier 90-nm SH7786 products were compatible with DDR2-SDRAM with an operating voltage of 1.8V.) In addition, the 65-nm processor’s multiple PCI Express bus interfaces support large-volume data transfers with data throughput up to 800MB/sec. This makes it possible to implement sophisticated drawing capabilities such as smoothing out complex and real 3D graphic images.
To aid the design of advanced multimedia equipment, a version of the E10A-USB on-chip debugging emulator with multi-core support is available as a development environment for the SH7786. It provides a range of flexible simultaneous debugging functions, including simultaneous execution, simultaneous break, and single-CPU break and re-execute. It greatly reduces the effort necessary to create software for systems that take full advantage of the 65-nm processor’s prodigious processing capabilities. The new SH7786 is fully supported by QNX® Neutrino® RTOS and the QNX Momentics® development suite.
About the dual SH-4A CPU cores
The architecture of the 65-nm SH7786 has two SH-4A CPU cores, each of which has a built-in floating-point processing unit (FPU), as well as its own cache memory and RAM. The design supports both symmetric multiprocessing (SMP) and asymmetric multiprocessing (AMP). For SMP, it implements a snoop controller that maintains the coherency of both CPUs’ internal caches by handling exchanges of cache update data between the cores.
The clock frequency and four low-power modes can be set independently for each CPU. For example, one CPU core can continue to operate at full speed while the other is set to a low-power mode. This enables to minimize power usage while responding quickly to changes in the SH7786’s processing load.
The FPUs in each CPU core operate at up to 533MHz and support both single-precision and double-precision arithmetic operations. Their maximum single-precision performance of 7.46 GFLOPS (giga floating-point operations per second) enables high-speed, high-quality codec processing of still images or MPEG video.
The internal cache memory of each CPU core is configured as a 32Kbyte four-way set-associative instruction cache and a 32Kbyte four-way set-associative data cache. Cache coherency support allows high-speed software processing. Also, each core’s 8Kbytes of RAM enables high-speed instruction fetches, while the 16Kbytes of RAM in each core enables high-speed data accesses. System engineers can boost the overall real-time performance of multimedia products by storing exception-handling routines in these on-chip RAM areas.
The SH7786 implements multiple PCI Express (PCIe) bus interfaces that can be set to operate as one to four lanes, for data transfers at up to 800MB/sec with external memory or other devices that have similar interfaces. A high-speed data transfer function is provided between lanes. This makes it possible, for example, to obtain high-level display capabilities by connecting a high-performance external display device that conforms to the PCIe bus connection specification. In addition, inexpensive standardized peripheral devices that support the PCIe interface can be used, a capability that offers expansion flexibility and helps reduce overall system cost.
About the SH7786’s on-chip peripheral functions
Built into the 65-nm SH7786 processor are the following functions:
* A USB 2.0 high-speed (480Mbps) host and function peripheral. It simplifies the development of systems with USB functionality and eliminates the need for a dedicated external USB 2.0 controller.
* A media access controller (MAC) conforming to the IEEE-802.3 standard. The MAC makes it easy to implement functionality for connecting to a 10/100Mbps (megabit per second) Ethernet LAN.
* Three low-power modes: Sleep, Light sleep, and Module standby. These modes can be controlled by software to reduce the power consumed by the chip to the lowest level consistent with the specific processing tasks being performed at any particular point in time.
* Additional peripherals, including display, sound and communication functions. They reduce the number of components required to build a multimedia system (see attached Specification Summary).
About development support for the dual-core SH7786 processor
When system engineers develop a multi-core product, they can allocate separate systems (domains) with different characteristics and functions to each CPU core. A distributed-function system design is used so the CPU cores can interoperate and function in an integrated manner. The SH7786 employs technologies developed by Renesas that support distributed-function system design approaches — specifically, communication interface technology for interoperability between the operating systems of multiple domains, and technology for preventing interference between the different operating systems. This enables developers to make use of existing software resources designed for single operating systems. It also enables to build multi-core distributed-function systems in a short amount of time. Additionally, these Renesas-developed technologies support different operating systems simultaneously with high levels of reliability.